1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a HEMT (High Electron Mobility Transistor) type semiconductor device.
2. Description of the Related Art
A conventional HEMT type semiconductor device comprises a semiconductor substrate, a buffer layer formed on the substrate, a semiconductor well layer (i.e., a channel layer or a carrier-flowing layer) formed on the buffer layer, a potential barrier layer forming an electric potential barrier against the carriers and formed on the well layer, and a gate electrode forming a Schottky contact and formed on the barrier layer. In the semiconductor well layer electrons (so-called two dimensional electron gas) are generated and flow at a high electron mobility, or holes (so-called two dimensional hole gas) are generated and flow at a high hole mobility. The substrate and formed layers are made of suitable compound semiconductor materials and form hetero-junctions at the interfaces between them. For example, the substrate and the well layer (channel layer) are of GaAs, InGaAs or InP, and the barrier layer is of AlGaAs or AlInAs.
Referring to FIG. 1, a conventional complementary HEMT type semiconductor device (C-HEMT) comprises, for example, a semiconductor substrate 51 of a semi-insulating GaAs substrate, a buffer layer 52 of undoped GaAs layer, a semiconductor well layer 53 of undoped In.sub.0.25 Ga.sub.0.5 As layer, and a potential barrier layer 55 of Al.sub.0.5 Ga.sub.0.75 As, the layers being formed by a continuous epitaxial growth process. To separate a p-channel HEMT and an n-channel HEMT from each other, an isolation region 61 is formed by ion-implanting B (boron) or O (oxygen) ions to the substrate 51 from the top surface of the potential barrier layer 55. On the barrier layer 55 first and second gate electrodes 62 and 63 are formed as Schottky barrier contacts and are surrounded by side-wall insulating films 64 and 65 of, e.g., SiO.sub.2, respectively. P-type (electrode) regions 56 and 57 are formed by selectively ion-implanting p-type impurities (e.g., Be) to the buffer layer 52 from the top surface of the potential barrier layer 55 by using the first gate electrode 62 and a suitable resist pattern layer (not shown) as a mask, and n-type (electrode) regions 58 and 59 are formed by selective ion-implanting n-type impurities (e.g, Si) in the layers 52, 53 and 55 by using the second gate electrode 63 and another suitable resist pattern layer as another mask. On the doped regions 56 and 57 p-type electrodes (not shown) are formed, on the doped regions 58 and 59 n-type electrode (not shown) are formed, and then these electrodes are electrically connected with suitable interconnections (e.g., wiring layers, not shown) to form an electric circuit.
In such a C-HEMT, a p-channel (i.e., two dimensional hole gas) is generated in a p-channel region 53p of a portion of the semiconductor well layer 53 between the p-type regions 56 and 57 and an n-channel (i.e., two dimensional electron gas) is generated in an n-channel region 53n of another portion of the semiconductor well layer 53 between the n-type regions 58 and 59.
A C-HEMT having the above-mentioned structure corresponds to a complementary III-V heterostructure FET (C-HFET) disclosed in an article by A. I. Akinwande et al. IEDM90, IEEE, 1990, pp. 983-986. The article discloses that a p-channel HFET (i.e., p-channel HEMT) has a threshold voltage of about -0.350 V (see Table 2) and an n-channel HFET (i.e., n-channel HEMT) has a threshold voltage of about 0.716 V (see Table 1). The sum (1.066 V) of the threshold voltages of the p-channel HEMT and n-channel HEMT corresponds to a bandgap of the semiconductor well layer 53. A drain current variation of each of the p-channel HEMT and n-channel HEMT, depending on the gate turn-on voltage, is obtained, as shown with a broken line in FIG. 2.
The conventional C-HEMT shown in FIG. 1 has, however, relatively high threshold voltages, and when absolute values of gate voltages applied on the gate electrodes are increased, gate leakage currents between the gate and source are generated and increased, as shown in FIG. 2. In such a case, when a logic amplitude is increased to maintain a high speed operation, the gate leakage current is also increased. Where the gate leakage current is suppressed, a gate voltage cannot be increased with the result that the high speed operation is not sufficiently attained. For example, at a power supply voltage of 1.5 V, a no-load gate delay is about 230 ps and power dissipation is about 64 .mu.W/gate, and at a power voltage of 1.0 V, a no-load gate delay is about 700 ps and power dissipation is about 7 .mu.W/gate (cf. the above-cited article, page 985, right column).
It is possible to adjust the threshold voltage of the n-HEMT to about zero volt by adding a threshold voltage controlling layer formed between the potential barrier layer and the gate electrode of the n-HEMT. In this case, it is necessary to make the controlling layer relatively thick, and thus a distance between the gate electrode and the semiconductor well layer becomes large, which deteriorates the controllability of the n-HEMT.
Another C-HEMT similar to that of FIG. 1 has been reported by R. R. Daniels et al. "Complementary Heterostructure Insulated Gate FET Circuits for High-Speed, Low Power VLSI", IEDM86, IEEE, 1986, pp. 448-451.
To lower the threshold voltages of the p-channel HEMT and n-channel HEMT, it is possible to form these HEMTs on the same semiconductor substrate such that a semiconductor laminated structure of the former HEMT is different from that of the latter HEMT. For example, Japanese Unexamined Patent Publication (Kokai) No. 57-208174 proposed a complementary FET utilizing a two dimensional electron gas and two dimensional hole gas; the FET of which comprises a p-channel HEMT having an undoped Ge layer, an undoped GaAs layer and a p-GaAs layer successively epitaxially grown on an undoped GaAlAs layer formed on a semi-insulating GaAs substrate; and an n-channel HEMT having an undoped GaAs layer, an undoped GaAlAs layer and an n-GaAlAs layer successively epitaxially grown on the undoped GaAlAs layer on the substrate, as shown in FIG. 9 thereof.